We have not written about RISC V much this year. Our sense was that there was not much news. Last year, it seemed like there was news every week, if not every day, coming out of the RISC V community. We attended the RISC V Summit late last year, and then things seemed to go quiet. So here we want to do a quick update on this “open” Instruction Set Architecture (ISA).
We have to admit, we were a bit concerned about that lack of news. The Summit demonstrated just how much work the community needed to do to bring the ecosystem up to speed, and so were worried about a diminishment in momentum. We now have a different view – RISC V work has been progressing, but it has entered a phase that is simultaneously important but also very boring. In the past, we have written at length about the difference between compiling software for RISC V (or any ISA) and optimizing that software for RISC V. Modern coding tools mean that coders can click a button and get code that runs on RISC V silicon, doing the proverbial 80% of the work. The problem is that last 20% is both critical to getting performant software and very boring to implement. This is low level, labor-intensive work that no one particularly likes to do. There is a lot of that taking place in the RISC V ecosystem now. There is a healthy amount of software running on RISC V today – many flavors of Linux, containers, databases and all the rest, but little of it runs at full speed. Advancing this work does not make for great headlines, but there is steady progress.
We came to this conclusion after learning about SiFive’s new processor the P870-D. SiFive is the commercial pioneer of RISC V chips, the first company to sell RISC V intellectual property (IP) and probably the leader in that market. Their business model is analogous to Arm’s in that they license IP to semis companies who then use that IP to design their own chips. SiFive also share’s Arm’s penchant for naming products in a less than fully decipherable fashion. The key to decoding the new processor’s name is that “-D” which stands for data center. This design is comparable to Arm’s Neoverse family of data center processors (and for those who really want to get in the weeds, this is comparable to Neoverse N, more than Neoverse V).
This is an important development for SiFive and RISC V. So far, RISC V has done best in the market for ’embedded’ semis – chips for industrial, IoT and consumer devices (other than phones and PCs). Those devices need a fairly low level of compute, and designers often have tighter cost concerns. By contrast, data center chips need to support a much higher level of compute.
There are several companies out there designing data center RISC V chips, and the P870-D could provide a big boost to their efforts. SiFive also has a fairly good reputation when it comes to commercializing products – this is not a science project and will have real customers in production next year. Most of the uses we have seen for RISC V in the data center market have been low-cost support cores in Arm-based systems on a chip. The fact that someone rates RISC V highly enough to merit a product like this is a fairly meaningful validation of the whole project.
That being said, for all the reasons we laid out at the top of this piece, RISC V still has a long road ahead of it in the data center. No one is switching away from Nvidia for this any time soon. But that is not really the point. Our view is that RISC V and Arm (and x86) will coexist in the data center for a very long time. Compute is getting more complicated and RISC V is now one more factor aiding and complexifying that trend.
It is too soon to judge the performance of the P870-D, but our guess is that it will prove competitive for many applications, maybe not the glamorous ones, but certainly some important ones. And this is just SiFive’s first generation, we expect them to keep advancing over time.
Leave a Reply